1. Field of the Invention
The present invention relates to non-volatile memory devices based on floating gate memory cells; and more particularly to flash EPROM or EEPROM integrated circuits adapted for storing fault tolerant data.
2. Description of Related Art
Non-volatile, integrated circuit memory devices based on floating gate transistors include devices known as electrically programmable read only memory EPROM, electrically erasable and programmable read only memory, EEPROM, and recently so-called flash memory. As the density of the floating gate devices has increased, making them more cost-effective, and as the programming and erasing speed has increased, this type of non-volatile memory has gained significant popularity. However, the process of programming data in a non-volatile memory device based on a floating gate, is still a relatively slow process. The process involves moving charge either into or out of the floating gate of the memory cell, in order to establish a data pattern in the array. Where the floating gate of a given cell is charged up with a population of electrons, the turn on threshold for the memory cell increases above the read gate voltage. Discharging the electrons from the floating gate moves the turn on threshold down below the read gate voltage. Thus, data may be written into the non-volatile memory array by processes which charge and discharge the floating gates.
The mechanisms for charging and discharging the floating gates in these devices include so-called hot electron injection, and so-called Fowler-Nordheim tunneling. Hot electron injection is used for increasing the charge in the floating gate by connecting the gate and the drain to a relatively high voltage, and the source to a relatively low voltage. Hot electrons in the resulting channel current are injected across the thin oxide which separates the floating gate from the channel. This results in an increase in charge in the floating gate. Alternatively, so-called Fowler-Nordheim tunneling can be used to program or erase the cell. The tunneling mechanism operates by establishing a large potential between the gate and the drain, source, or channel. The Fowler-Nordheim tunneling effect results in charge tunneling through the thin oxide which isolates the floating gate. The Fowler-Nordheim tunneling process is relatively slow compared to the hot electron injection process. However, hot electron injection utilizes higher current. Further, hot electron injection cannot be used for discharging the floating gate. Rather, the tunneling mechanism is most often used for the discharging process.
The tunneling and hot electron injection mechanisms used for programming and erasing cells in a floating gate device do not affect each cell in the array identically. Therefore, the programming and erasing functions on modern floating gate devices include erase and program verify algorithms. After a programming or erasing operation, the memory subject of the operation is verified. If any cell fails the verify process, then a re-program or re-erase process is executed. This process is re-tried a large number of times (as many as 1000 times or more in some devices) in order to ensure that all of the data in the array is accurately stored, and to prevent having to discard floating gate devices which would otherwise operate satisfactorily, except for the number of retries required to program or erase the cells.
The program and erase verify procedures involved in these devices are relatively time consuming. Therefore, the use of flash memory or other floating gate memory devices for real time storage applications has been limited. In a real time application, an incoming stream may supply more data than the flash memory device is capable of storing without being overrun. Therefore, real time applications in the past have relied on dynamic RAM, SRAM, or other reliable fast memory techniques. However, these prior art memory techniques are not non-volatile, and data can be lost if there is an interruption in power.
Prior art flash memory systems for sequential data such as described in U.S. Pat. No. 5,200,959, invented by Gross, et al., have mapped defects byte by byte in a floating gate array, and stored the defect map in the floating gate array itself. Using the defect map, future operations may avoid defective areas in the device, improving performance and device endurance (see column 8, line 62 to column 9, line 16 of Gross, et al.). This is useful for applications which are not time critical, and tolerate no errors. However, in time critical operations or operations in which there is insufficient buffer memory, the extra time involved in generating and storing defect maps makes the devices impractical for fast sequential data streams.
Accordingly, it is desirable to provide a floating gate memory device architecture, such as high density flash memory, which is capable of storing a time critical data stream, and which is low cost and fault tolerant.